Resistance variable memory elements, which include Programmable Conductive Random Access Memory (PCRAM) elements, have been investigated for suitability as semi-volatile and non-volatile random access memory devices. In a typical PCRAM device, the conductivity/resistance of a chalcogenide glass backbone can be programmed to stable lower conductivity (i.e., higher resistance) and higher conductivity (i.e., lower resistance) states. An unprogrammed PCRAM device is normally in a lower conductivity, higher resistance state.
A conditioning operation forms a conducting channel of a metal-chalcogenide in the PCRAM device, which supports a conductive pathway for altering the conductivity/resistivity state of the device. After the conditioning operation, a write operation will program the PCRAM device to a higher conductivity state, in which metal ions accumulate along the conducting channel(s). The PCRAM device may be read by applying a voltage of a lesser magnitude than required to program it; the current or resistance across the memory device is sensed as higher or lower to define the logic “one” and “zero” states. The PCRAM may be erased by applying a reverse voltage (opposite bias) relative to the write voltage, which disrupts the conductive pathway, but typically leaves the conducting channel intact. In this way, such a device can function as a variable resistance memory having at least two conductivity states, which can define two respective logic states, i.e., at least a bit of data.
FIG. 1 illustrates a portion of a memory device 10 utilizing resistance variable memory elements as memory cells 120, 121. For exemplary purposes, PCRAM elements are used as the cells 120, 121. Each memory cell 120, 121 has a cell plate connected to a cell plate potential CPIN and is connected to a respective access transistor 140, 141. The first access transistor 140 is connected between the first memory cell 120 and a first digit line DIGIT. The second access transistor 141 is connected between the second memory cell 121 and a second digit line DIGIT. The gates of the access transistors 140, 141 are connected to word lines WL0, WL1 such that they receive row select signals R0, R1, respectively.
The device 10 also includes sensing circuitry 30 connected to the digit lines DIGIT, DIGIT. The sensing circuitry 30 includes an equilibration circuit 32, two column select transistors 42, 44, a reference voltage circuit 50, two isolating transistors 62, 64, a p-sense amplifier driver 78, a p-sense amplifier circuit 70, an n-sense amplifier driver 88 and an n-sense amplifier circuit 80.
The equilibration (EQ) circuit 32 includes three EQ transistors 34, 36, 38. The first EQ transistor 34 is connected between the two digit lines DIGIT, DIGIT. The second EQ transistor 36 is connected between the first digit line DIGIT and the third EQ transistor 38. The third EQ transistor 38 is connected between the second digit line DIGIT and the second EQ transistor 36. The gate terminals of the three EQ transistors 34, 36, 38 are connected to an equilibration gating line EQ. A bias voltage DVC2 is applied at the connection of the second and third EQ transistors 36, 38. All three of the EQ transistors 34, 36, 38 are NMOS transistors. The equilibration circuit 32, in response to the equilibration gating signal EQ, effectively equalizes the charges held by the digit lines DIGIT, DIGIT after a read/write operation is completed and when the memory array is not active.
The first column select transistor 42 has its source and drain terminals connected between the first digit line DIGIT. The second column select transistor 44 has its source and drain terminals connected between the second digit line DIGIT. The gates of the column select transistors 42, 44 are connected to respective column select lines to receive a column select signal CSEL. The column select transistors 42, 44 are activated by the column select signal CSEL when it is desired to connect the remaining circuitry of the sensing circuitry 30 to the memory cells 120, 121 (such as for example when it is time to write, erase or read the cells 120, 121).
The reference voltage circuit 50 includes 4 reference voltage transistors 52, 54, 56, 58. The first reference voltage transistor 52 is connected between the first digit line DIGIT and the second reference voltage transistor 54. The second reference voltage transistor 54 is connected between the first reference voltage transistor 52 and the second digit line DIGIT. DVC2 is applied to the connection between the first and second reference voltage transistors 52, 54. The third reference voltage transistor 56 is connected between the first digit line DIGIT and the fourth reference voltage transistor 58. The fourth reference voltage transistor 58 is connected between the third reference voltage transistor 56 and the second digit line DIGIT. A reference voltage VREF is applied to the connection between the third and fourth reference voltage transistors 56, 58.
The gate of the first reference voltage transistor 52 is connected to the gate of the fourth reference voltage transistor 58 and to a first reference voltage signal REF E. The gate of the second reference voltage transistor 54 is connected to the gate of the third reference voltage transistor 56 and to a second reference voltage signal REF O. The operation of the reference voltage circuit 50 is explained below in more detail.
The first isolating transistor 62 is connected between the first digit line DIGIT and a first connection between the p-sense amplifier circuit 70 and the n-sense amplifier circuit 80. The second isolating transistor 64 is connected between the second digit line DIGIT and a second connection between the p-sense amplifier circuit 70 and the n-sense amplifier circuit 80. The gate terminals of the first and second isolating transistors 62, 64 are connected to an isolation gating signal SA ISO. The illustrated isolating transistors 62, 64 are NMOS transistors. The isolating transistors 62, 64, when activated by the isolation gating signal SA ISO, form isolation devices that effectively remove certain portions of the circuit 30 during addressing for a portion of a read and during a write and erase.
The p-sense amplifier circuit 70 includes two PMOS transistors 72, 74. The n-sense amplifier circuit 80 includes two NMOS transistors 82, 84. The first PMOS transistor 72 has its gate terminal connected to the second digit line DIGIT and is connected between the first NMOS transistor 82 and the p-sense amplifier driver 78. The second PMOS transistor 74 has its gate terminal connected to the first digit line DIGIT and is connected between the second NMOS transistor 84 and driver 78. The p-sense amplifier driver 78 drives the p-sense amplifier 70 when a p-sense amplifier latching signal PL is applied to the gate of the driver 78.
The first NMOS transistor 82 has its gate terminal connected to the second digit line DIGIT and is connected between the n-sense amplifier driver 88 and the first PMOS transistor 72. The second NMOS transistor 84 has its gate terminal connected to the first digit line DIGIT and is connected between driver 88 and the second PMOS transistor 74. The n-sense amplifier driver 88 drives the n-sense amplifier 80 when an n-sense amplifier latching signal NL is applied to the gate of the driver 88.
Two write/erase circuits 920, 921 are respectively connected to the digit lines DIGIT, DIGIT via the sensing circuitry 30. The write/erase circuits 920, 921 apply a first programming voltage VPNS to the digit lines DIGIT, DIGIT when the cells 120 or 121 are to be written to the high conductivity (i.e., lower resistance) state (as described above) depending on which row R1, R0 is accessed. The write/erase circuits 920, 921 apply a second programming voltage VPPS, typically a reverse voltage (i.e., opposite bias) relative to the first programming voltage VPNS, to the digit lines DIGIT, DIGIT when the cells 120 or 121 are to be written to the lower conductivity (i.e., higher resistance) state (as described above) depending on which row R1 or R0 is accessed. The appropriate column select transistors 42, 44 will also need to be activated during the write and erase operations.
To read the first memory cell 120, for example, the first reference signal REF E is generated, which causes the reference voltage circuit 50 to precharge the first digit line DIGIT to DVC2 (via an activated first column select transistor 42). In addition, the reference voltage circuit 50 precharges the second digit line DIGIT to the reference voltage VREF. These precharged values will be applied to the digit lines and to the p-sense amplifier 70 and n-sense amplifier 80 (via activated isolation transistor 64). The current across the memory cell 120 is sensed by p-sense amplifier 70 and n-sense amplifier 80 (via activated isolation transistor 62) and compared to the reference voltage VREF to determine the state of the memory cell 120 once the access transistor 140 is turned on.
Similarly, to read the second memory cell 121, the second reference signal REF O is generated, which causes the reference voltage circuit 50 to apply DVC2 to the second digit line DIGIT (via an activated second column select transistor 44 and access transistor 141). In addition, the reference voltage circuit 50 applies the reference voltage VREF to the first digit line, DIGIT. Again, these precharged values will be applied to the digit lines and to the p-sense amplifier 70 and n-sense amplifier 80 (via activated isolation transistor 62). The current across the memory cell 121 is sensed by p-sense amplifier 70 and n-sense amplifier 80 (via activated isolation transistor 64) and compared to the reference voltage VREF to determine the state of the memory cell 121 once the access transistor 141 is turned on.
Under the current architecture, PCRAM cells, such as e.g., cells 120, 121, can only sustain approximately a 200 mV potential across the cell before a partial erase or write occurs. Changes in the cell plate potential CPIN and the digit line programming voltages VPPS, VPNS allow an addressed cell to be written to or erased. The drawback, however, is that with different potentials for the cell plate and the equilibrated digit lines, non-addressed cells on the same word line may also become partially erased or written.
Typically, a written cell would cause its digit line voltage to approach CPIN, while an erased cell would cause its digit line voltage to approach DVC2. The p-sense amplifier 70 and n-sense amplifier 80 of the sensing circuitry 30 attempts to differentiate the digit line potential from the reference voltage VREF, which is applied to the complementary digit line. FIG. 2 illustrates a graph of sense time v. digit line voltage for the memory device 10 illustrated in FIG. 1. Line 102 represents the digit line voltage for a written cell. Line 104 represents the digit line voltage for an erased cell. If DVC2 is 1.0V (line 110) and CPIN is 1.2V (line 106), VREF is 1.1V (line 108). This leaves at most 100 mV of sensing differential at the time the sense amplifiers are latched (e.g., at approximately 150 nS). Most likely, there is approximately a 60 mV differential when the cell is written and about a 40 mV differential when the cell is erased.
There is a need and desire to increase the sensing window for a resistance variable memory device such as e.g., a PCRAM memory device. There is also a need and desire to increase the sensing window without causing the potential across the cell to be greater than approximately 200 mV.
There is also a need and desire to write to resistance variable memory cells while keeping the voltage across non-addressed cells at approximately 0V. There is also a need and desire to sense the state of resistance variable memory cells closer in time when the cells are accessed, in comparison to typical sensing techniques.